The present invention relates to memory devices and methods of operating the same and, more particularly, to nonvolatile flash memory devices and methods of operating the same.
Nonvolatile flash memory devices are types of electrically erasable and programmable read-only memories (EEPROMs) in which pluralities of memory regions may be erased or written with data in a one-time programming operation. A typical traditional EEPROM, however, may be configured such that only one memory region is erasable or programmable at a time. This means that flash memories may operate more rapidly and effectively in reading and writing data when systems employing them read/write data from/into different memory regions at the same time. Commonly, flash memories or EEPROMs are configured such that insulation films enclosing charge storage elements used for storing data are worn out after the specific number of operations.
Flash memories typically retain stored information even without power supply. In other words, flash memories typically are able to retain their information without power consumption even when power to the chip is interrupted. Additionally, flash memories may be relatively resistant to physical impacts, offering fast accessibility for reading. With those advantageous properties, the flash memories are commonly used as storage units in battery-powered devices.
A typical flash memory device is configured to store information in an array of transistors that are called cells, each cell configured to store at least 1-bit of data. A multi-level cell (MLC) flash memory device may be capable of storing more than 1 bit by varying an amount of charge accumulated in floating gate of a memory cell.
In a flash memory device using floating gate technology, data retention characteristics and endurance (the permissible number of programming/erasing cycles without degradation in operation quality) are generally important. Charge (electrons) accumulated in a floating gate may leak out due to various fail mechanisms, such as thermal ion release and charge diffusion through defective an inter-poly insulation film, ionic impurities, stress due to program disturbance, and other mechanisms. Such leakage of charge may result in reduction of threshold voltage.
When a power source voltage is applied to a control gate of a flash memory cell, charge acquisition may occur, which may lead to an elevation of threshold voltage. Repetitive programming/erasing cycles may force oxide films of memory transistors to be stressed, generating failures, such as tunnel oxide breakdown, in the flash memory device. Threshold voltages of memory cells gradually decline due to the stress. In other words, charges may more easily leak from the floating gates of programmed memory cells due to the stress to the oxide films. As a result, a threshold voltage distribution of the programmed memory cells may shift, which may cause some memory cells to have a threshold voltage less than a program-verifying voltage. This can result in a read failure due to reduction of read margin.